The present invention generally relates to semiconductor processing, and in particular to systems and methods for monitoring and regulating the concentration of nitrogen in a nitrided gate oxide layer.
In the semiconductor industry, there is a continuing trend toward manufacturing integrated circuits with a greater number of layers and with higher device densities. To achieve these high densities there have been, and continue to be, efforts towards reducing the thickness of layers, improving the uniformity of layers, reducing the thickness of devices and scaling down device dimensions (e.g., at sub micron levels) on semiconductor wafers. In order to accomplish higher device packing densities, thinner layers, more uniform layers, smaller feature sizes, and smaller separations between features are required. This can include the width and/or thickness of gate oxide materials, (e.g., silicon oxide, silicon nitride, silicon oxynitride, high K metal oxides), interconnecting lines, spacing and diameter of contact holes, and the surface geometry such as corners and edges of various features.
But as lateral device dimensions are scaled deeply into the sub-micron range, as required to achieve desired speed and integration improvements, corresponding reductions in gate-oxide thickness can have undesired impacts. For example, problems associated with direct tunneling can occur when gate oxide thickness decreases below certain thresholds. For example, as the gate oxide thickness is reduced into the sub-two nanometer region, a rapid increase in direct tunneling and boron penetration in PMOS devices can be a major obstacle for device scaling.
The process of manufacturing semiconductors, or integrated circuits (commonly called ICs, or chips), typically consists of more than a hundred steps, during which hundreds of copies of an integrated circuit can be formed on a single wafer. Generally, the process involves creating several layers on and/or in a substrate that ultimately forms the complete integrated circuit. This layering process can create electrically active regions in and/or on the semiconductor wafer surface. Insulation and conductivity between such electrically active regions can be important to reliable operation of such integrated circuits. Thus, controlling the width and/or uniformity of layers created during the layering process can be important to the reliable operation of such integrated circuits. Further, the insulating and/or conducting properties of a layer can be affected by the chemical composition of a layer (e.g., the concentration of one or more elements). One type of integrated circuit in which insulation and conductivity between electrically active regions is important is electronic memory.
Electronic memory comes in different forms to serve different purposes. One such electronic memory, flash memory can be employed for information storage in devices including, but not limited to, voice recorders, cellular phones, digital cameras and home video game consoles. Flash memory can be considered a solid-state storage device, in that functionality is achieved electronically rather than mechanically. Flash memory is a type of EEPROM (Electrically Erasable Programmable Read Only Memory) chip. Flash memories are a type of non-volatile memory (NVM). NVMs can retain information when power to the NVM is removed in contrast to NVMs with volatile memories (e.g., DRAM, SRAM) that lose stored data when power is removed. Flash memory is electrically erasable and re-programmable in-system. The combination of non-volatility and in-system eraseability/re-programmability make flash memory well-suited to a number of end-product applications including, but not limited to, personal computer BIOS, telecom switches, cellular phones, internetworking devices, instrumentation, automotive devices and consumer-oriented voice, image and data storage devices (e.g., digital cameras, digital voice recorders, PDAs).
An exemplary MOSFET 100 (Metal Oxide Semiconductor Field Effect Transistor), another semiconductor device, is illustrated in Prior Art. FIG. 1. The exemplary MOSFET device 100 illustrated includes a gate 104 separated from a substrate 110 by a gate oxide 102. The MOSFET includes a source 106 and a drain 108. The components of the thin gate oxide 102 can be important to reliable operation of the MOSFET 100, and thus, manufacturing the gate oxide 102 with desired components to precise measurements facilitates increasing MOSFET reliability.
The gate oxide layer 102 functions as an insulating layer. The gate oxide layer 102 can be the smallest feature of a device. Controlling the components of the gate oxide layer 102 can contribute to increasing the switching speed of a transistor. Thus, precisely monitoring and controlling properties of the gate oxide layer 102 including, but not limited to, relative material concentration, are important to facilitating reliable operation of the MOSFET 100. For example, the ability to store data, to retain data, to be erased, to be reprogrammed and to operate in desired electrical and temperature ranges can be affected by the components that constitute the gate oxide layer 102.
In deep submicron CMOS technology to improve the reliability of ultra-thin gate oxides and also to prevent boron penetration from the poly gate, different nitridation techniques are used to incorporate nitrogen into gate oxides. Nitridation can be done by in situ or post annealing of oxides in an ambient of nitric oxide (NO), nitrous oxide, or ammonia. Alternate techniques include implanting nitrogen into the gate oxides. The nitridation process can be done in batch type furnace or in a single wafer processing cluster tool. Stacked gate oxides are also prepared by depositing a thin nitride layer on an oxide. Plasma nitridation techniques such as RPN (remote plasma nitridation) and DPN (decoupled plasma nitridation) are also employed for nitridation.
The insulating properties of the gate oxide layer 102 can be affected not only by its thickness but by the chemical composition of the gate oxide layer 102, including the concentration of nitrogen. Precisely controlling the gate oxide thickness and composition (such as nitrogen concentration) are required to maintain current levels required for circuit operation in devices employing a gate oxide layer 102.
Properties of the gate oxide layer 102 including, but not limited to, chemical composition (e.g., nitrogen concentration), thickness and uniformity can affect the operation of one or more MOSFETs fabricated on the gate oxide layer 102. It is to be appreciated that the present invention can be applied to the formation of gate oxide layers in other integrated circuits. For example, the present invention can be applied to all (for example in DRAM, SRAM, and other memory devices, microprocessors, logic circuits and tunnel oxides in EEPROM type flash memory devices and SONOS type flash memory devices) CMOS devices where thin nitrided gate oxides are used. The technique can also be applied to oxynitrides, or oxide/nitride type stacked gate oxides.
The requirement of small features with close spacing between adjacent features in semiconductor devices with submicron geometry requires sophisticated manufacturing techniques including precise control of gate oxide layer formation. By way of illustration, fabricating microprocessor or memory devices using such sophisticated techniques may involve a series of steps including the formation of layers/structures by chemical vapor deposition (CVD), rapid thermal oxidation and oxide growth. Conventionally, difficulties in forming ultra thin gate oxide layers, with precise nitrogen concentration, have limited the effectiveness and/or reliability of such devices manufactured by conventional techniques. By way of further illustration, for CMOS devices, similar gate oxide considerations can apply to at least two different portions of a gate dielectric structure: the Sixe2x80x94SiO2 interface and the bulk of dielectric film. The Sixe2x80x94SiO2 interfaces for CMOS devices may be formed by methods including, but not limited to, thermal oxidation of the Si substrate (wherein the Sixe2x80x94SiO2 interface is continuously regenerated and buried beneath the surface of the Si wafer), ideal deposition processes (where the metallurgical boundary between the Si and the deposited SiO2 film is maintained at the original surface of the Si), real deposition processes, (where plasma or thermally generated, chemically active oxygen species interact with the Si substrate during deposition to facilitate oxidation occurring at the Si substrate during initial deposition to displace the Sixe2x80x94SiO2 interface into the bulk of the Si substrate layer) and by a two-step plasma oxidation/deposition (where a thin passivating layer of SiO2 is created during a remote-plasma-assisted oxidation (RPAO) phase to form the interface and to prevent further oxidation of the Si substrate during oxide deposition by remote-plasma-enhanced chemical vapor deposition (RPECVD). After gate oxides are prepared by any these techniques, nitridation of gate oxide can be performed by any of the techniques described earlier to incorporate nitrogen into the gate oxide either at Si/SiO2 interface or in the bulk of the gate oxide.
Due to the extremely fine structures that are fabricated in submicron CMOS devices (beyond 0.25 micron technology) controlling the formation of gate oxide materials used to form a gate oxide layer are significant factors in achieving desired critical dimensions and operating properties and thus in manufacturing reliable devices. The more precisely the gate oxide layer can be formed, including the more precisely the concentration of chemicals that contribute to a gate oxide equivalent thickness calculation can be controlled, the more precisely critical dimensions may be achieved, with a corresponding increase in reliability. Similarly, more precisely a gate oxide layer can be formed, including monitoring thickness and chemical concentration affecting equivalent thickness, the higher quality and more reliable CMOS devices can be fabricated.
Conventionally, due to non-uniform gate oxide layer formation and inaccurate gate oxide layer formation monitoring techniques, a thickness of gate oxide greater or lesser than the thickness desired may be formed. Similarly, due to inaccurate chemical composition monitoring, undesired concentrations of chemicals (such as concentration of nitrogen and oxygen) negatively affecting oxide equivalent thickness may be generated.
This section presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is not intended to identify key/critical elements of the invention nor is it intended to delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention provides for a system that facilitates monitoring and controlling nitrided gate oxide layer formation. In particular, the present invention provides for monitoring the concentration of nitrogen (N) employed in nitriding a gate oxide layer to affect the equivalent gate oxide thickness of a nitrided gate oxide layer. Such nitrided gate oxide layers may be employed in devices including, but not limited to, microprocessors, logic devices, EEPROMs (e.g., flash memory), volatile memories (e.g., DRAM, SRAM) and other memory devices. The present invention is also applicable to gate oxides that employ high K metal oxides, where a thin nitrided layer is used as a top or bottom interface, and also to oxide/nitride gate stacks. An exemplary system may employ one or more light sources arranged to project light on one or more nitrided gate oxide layers on a wafer and one or more light sensing devices (e.g., photo detector, photo diode) for detecting light reflected by the one or more gate oxide layers. The light reflected from one or more nitrided gate oxide layers is indicative of at least nitrided gate oxide layer nitrogen concentration, which may vary during the gate oxide layer formation process.
One or more nitrided gate oxide layer formers can be arranged to correspond to a particular wafer portion. Each nitrided gate oxide layer former may be responsible for forming a nitrided gate oxide layer on one or more particular wafer portions. The nitrided gate oxide layer formers may be responsible for introducing nitrogen into the nitrided gate oxide layer. Precisely controlling the amount of nitrogen in the nitrided gate oxide layer can improve the performance of the nitrided gate oxide layer. Thus, the present invention facilitates precisely forming nitrided gate oxide layers that include precise concentrations of nitrogen, where the nitrogen concentration may be between one percent and ninety-nine percent nitrogen. The nitrided gate oxide layer more be formed by techniques including, but not limited to, chemical vapor deposition with nitrogen, growth over a thin oxide and annealing with nitrogen in the atmosphere. The nitrided gate oxide layer formers are selectively driven by the system to form a nitrided gate oxide layer on one or more particular wafer portions with a desired nitrogen concentration and/or a desired thickness and/or uniformity. The progress of the nitrided gate oxide layer formation is monitored by the system by comparing the concentration of chemicals affecting equivalent gate oxide thickness (e.g., nitrogen, silicon and/or oxygen) of the nitrided gate oxide layer on a wafer to a desired concentration. Different wafers and even different components within a wafer may benefit from varying nitrogen concentrations. Furthermore, the nitrided gate oxide layers may be involved in different nitridations of the nitrided gate oxides including, but not limited to, interfacial nitridation and top-surface nitridation. By monitoring nitrided gale oxide nitrogen concentration at one or more wafer portions, the present invention enables selective control of nitrided gate oxide formation. As a result, more optimal nitrided gate oxide formation is achieved, which in turn improves flash memory manufacturing. Similarly, such optimal nitrided gate oxide formation improves performance and reliability of other devices employing nitrided gate oxides (e.g., CMOS devices).
One particular aspect of the invention relates to a system for regulating nitrided gate oxide layer formation in submicron CMOS devices beyond 0.25 micron technology. The system includes a nitrided gate oxide former operative to form a nitrided gate oxide layer on a portion of a wafer. The nitrided gate oxide layer can be formed from materials including, but not limited to, silicon oxide, nitrogen, silicon nitride, and silicon oxynitride. The nitrided gate oxide layer can be of an oxide equivalent thickness down to less than three nanometers. Below the thickness of about two nanometers in an SiO2 gate oxide film, direct tunneling becomes the dominant mechanism for current transport through the film. It is desirable for gate dielectric manufacturing to reduce direct tunneling while maintaining an oxide-equivalent thickness corresponding to a thinner SiO2 film. Incorporating nitrogen into the gate oxide film can facilitate a reduction of leakage current of gate oxide.
The system also includes a nitrided gate oxide former driving system for driving a nitrided gate oxide former and a system for directing light on to a portion of the wafer. The system further includes a measuring system for measuring parameters of nitrided gate oxide formation nitrogen concentration based on light reflected from nitrided gate oxide formations and a processor that receives nitrided gate oxide formation nitrogen concentration data from the measuring system. The processor uses the data to generate feedback information that can be employed to base control of a nitrided gate oxide former so as to regulate nitrided gate oxide nitrogen concentration on the portion of the wafer.
Another aspect of the present invention provides a method for regulating nitrided gate oxide layer formation. The method includes defining a wafer as a plurality of portions and establishing one or more nitrided gate oxide layer formations to be formed in the one or more portions. The method further includes directing light onto the nitrided gate oxide layer formations, collecting light reflected from the nitrided gate oxide layer formations and analyzing the reflected light to determine nitrogen concentration of the nitrided gate oxide layer formation. Once the reflected light has been analyzed, the method proceeds to generating feedback information that can be employed in controlling nitrided gate oxide layer formers to regulate nitrided gate oxide formation.
To the accomplishment of the foregoing and related ends, the invention, then, comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the invention. These aspects are indicative of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.